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COMPUTER MEMORY
Flash memory
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| Type | Non-volatile semiconductor memory[1] | ||||||||||
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| Invented | 1984 (NOR); 1987 (NAND)[2] | ||||||||||
| Inventor | Fujio Masuoka, at Toshiba[2][3] | ||||||||||
| Cell | One transistor with an isolated charge store[1] | ||||||||||
| Two types | NOR (random access, code) NAND (dense, bulk storage)[4] | ||||||||||
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Flash memory is a kind of computer memory that keeps its contents when the power is switched off, and that can be erased and rewritten electrically. It is the storage inside every smartphone, memory card, USB stick and solid-state drive, and it has largely replaced the spinning hard disk in personal computers.[4][1] Unlike DRAM, which forgets everything the instant it loses power, flash holds data for years without any electricity at all.[1]
Each cell is a single transistor with an extra store of charge sealed inside its insulating layers. Adding or removing electrons from that store changes the voltage at which the transistor switches on, and the chip reads a cell by testing which way it behaves. Because the store is surrounded by insulator, the charge stays put with the power off — that is what makes the memory non-volatile.[1][9]
The name comes from how it is erased. Flash gives up the ability to rewrite one byte at a time, and instead wipes a large block all at once. That sounds like a step backwards, but it removed the extra transistor each cell had needed, which shrank the cell to a single transistor and cut the cost per bit dramatically.[10][2] Cheapness is the whole point of flash, and every design decision in it follows from that.
Flash was invented by Fujio Masuoka at Toshiba, who presented the first version in 1984 and the far denser NAND arrangement in 1987.[2][11] The market it created is now enormous. Flash revenue reached US$69.7 billion in 2025, and TrendForce projects US$147.3 billion for 2026 as artificial-intelligence data centres buy storage faster than the industry can build it.[12]
A flash cell is an ordinary transistor with one addition: a second gate, buried in the insulator between the control gate and the current-carrying channel, with no electrical connection to anything.[1][13] Electrons pushed into that hidden store partly cancel the voltage applied from outside, so the transistor needs a higher voltage than usual before it will conduct. Reading a cell means applying a test voltage and seeing whether current flows.[1][9]
The original design used a conducting layer, called a floating gate. Newer chips use charge-trap flash instead, holding the electrons in an insulating silicon nitride layer. An insulating store cannot leak its charge sideways into a neighbouring cell, which is what allowed the industry to keep packing cells closer together.[14]
Getting electrons through a solid insulator relies on quantum mechanics. Under a strong enough electric field they tunnel straight through the barrier, an effect named Fowler–Nordheim tunnelling. NAND flash uses it for both writing and erasing; NOR flash writes by firing energetic electrons at the store instead, and erases by tunnelling.[9][15][13]
This is the structural fact that shapes everything built on flash. A chip is read and written a page at a time, typically 8 to 16 kilobytes, but it can only be erased a whole block at a time, and a block holds hundreds of pages.[9][5] Writing can only turn bits one way; returning them requires an erase.[5]
The consequence is that data cannot be changed where it sits. To alter a few bytes, the drive writes a fresh copy somewhere else, marks the old page invalid, and deals with the mess later.[9] Everything awkward about flash — the controller software, the wear management, the sudden slowdowns on a full drive — traces back to this one rule.
A cell does not have to hold just one bit. By charging the store to several distinguishable levels, a manufacturer can read more than one bit out of the same transistor. Single-level cells hold one bit, multi-level two, triple-level three and quad-level four; a five-bit version needs 32 separate voltage levels and has been demonstrated but is not widely sold.[6][16]
Each extra bit buys roughly a third more capacity from the same silicon, which is why almost all consumer storage is now triple- or quad-level.[6] The cost is that the voltage levels sit closer together, so the cell tolerates less drift, wears out sooner and is slower to write.[6][9]
Masuoka's two designs differ in how the cells are wired together, and they ended up serving quite different markets.
NOR flash connects each cell so that it can be reached on its own. That allows true random access to any byte, and a processor can run code directly out of a NOR chip without copying it into memory first — the reason NOR is still used for the boot firmware in cars, industrial controllers and network equipment. It reads in a fraction of a microsecond but is comparatively bulky, and parts run from about 128 megabits to 2 gigabits.[4][5]
NAND wires cells in series, in strings, which removes most of the contacts and makes each cell about 60% smaller.[5] The price is that data must be reached serially and in pages rather than bytes, so NAND takes tens of microseconds to produce its first byte. In exchange it is enormously denser and cheaper, reaching terabits per chip, and it is what all bulk storage is built from.[5][4]
The speed gap to other technologies is wide in both directions. NAND reads take around 25 microseconds and writes several hundred, against tens of nanoseconds for DRAM and around ten milliseconds for a mechanical hard disk.[5][17] Flash therefore sits in the gap between memory and disk, closer to memory in speed and closer to disk in price.
Flash wears out. Every erase drives electrons through the thin oxide layer around the charge store, and each pass leaves a little damage behind. Traps accumulate in the oxide, the cell holds charge less reliably, and eventually the block has to be retired.[9][18] Manufacturers rate parts in program–erase cycles. Single-level NAND is specified at about 100,000 and older two-bit parts at around 5,000; flat three-bit parts managed roughly 1,000, though stacked designs have raised that figure considerably.[5][18][9]
Three other effects degrade stored data. Reading one row nudges the charge in its neighbours, and so does writing; and charge simply leaks away over time, faster when the chip is hot. The margins are startlingly small — a cell in a leading-edge planar chip stored only about a hundred electrons.[9] Manufacturers generally specify ten years of retention for NAND.[18]
A drive is therefore mostly software. Its controller runs a flash translation layer, which maps the addresses the computer uses onto wherever the data physically sits. That layer spreads writes evenly across the chips so no block wears out early, collects scattered valid pages together so blocks can be freed, and keeps spare capacity in reserve that the user never sees.[9] The TRIM command lets the operating system tell the drive which data it has deleted, so the controller stops carefully preserving files that no longer exist.[19]
All of that housekeeping means a drive writes more to the flash than the computer asked it to, a ratio known as write amplification.[9] Raw flash is also error-prone by design, and every drive corrects errors continuously. The older BCH codes have given way to LDPC codes, which tolerate roughly three times the raw error rate for the same final reliability — a necessity as cells became less dependable.[9][20]
Non-volatile memory existed before flash but was awkward to use. The erasable programmable read-only memory, invented by Dov Frohman at Intel in 1971, stored charge on a floating gate and was erased by shining ultraviolet light through a quartz window in the chip package.[21] Electrically erasable versions followed at the end of the 1970s and removed the light source, but they needed two transistors per cell in order to select individual bytes, which made them expensive.[21][10]
Fujio Masuoka was responsible for memory design at Toshiba when, in 1980, he put a small team to work on a cheaper non-volatile cell.[11][10] His answer was to abandon byte-by-byte erasing. If the whole chip could be wiped at once, the select transistor was unnecessary, and one transistor per cell was enough.[10] He presented the design at the IEEE International Electron Devices Meeting in San Francisco in December 1984.[11][3]
The name was suggested by a colleague, Shoji Ariizumi, who said that wiping the whole chip at once reminded him of a camera flash.[11][3] Toshiba did not pursue the 1984 design, which was hard to manufacture.[3] Masuoka returned in 1987 with the NAND arrangement, presented at that year's IEDM in Washington, which strung cells together to cut the cell area much further.[11][2]
Toshiba was slow to back him. The company only committed to production after Intel launched a commercial NOR flash chip in 1988 and demonstrated that a market existed.[10][22] Toshiba brought out the first commercial NAND chip, holding four megabits, in 1991.[2] Masuoka left for a professorship at Tohoku University in 1994 and later sued Toshiba over his share of the proceeds, settling in 2006 for a one-off payment of ¥87 million.[23][10] He received the IEEE Morris N. Liebmann Memorial Award in 1997 and the Honda Prize in 2018.[24][25]
The other founding company was SunDisk, later SanDisk, started in 1988 by Eli Harari with Sanjay Mehrotra and Jack Yuan. Harari's patent that year covered not just a cell but a complete storage system, with a controller that found and worked around defective cells — the idea that made flash usable as a disk replacement.[3][26] The company built a prototype solid-state drive for IBM in 1991.[26]
Consumer formats followed. SanDisk introduced CompactFlash in 1994 and it quickly became the standard card for digital cameras.[27] Toshiba announced its own card format in 1995.[28] Panasonic, SanDisk and Toshiba then founded the SD Association in January 2000 to promote a smaller card of their joint design; the first SD cards held eight megabytes.[29][30]
The USB flash drive appeared around 2000, and who invented it is still disputed. Teams at M-Systems in Israel, Trek 2000 in Singapore, Netac in China and IBM all have claims, with patent filings within months of one another.[31] Toshiba shipped the first two-bit-per-cell NAND in 2001, beginning the long trade of endurance for capacity.[2] Portable music players and then smartphones turned flash into a mass-market commodity; Apple's first iPhone in 2007 ran on it, and the company signed long-term supply agreements to secure it.[32]
By around 2010 flat NAND was running out of room. Shrinking a cell left it holding too few electrons to read reliably, and packed cells so close that each interfered with its neighbours.[33] The industry's answer was to stop shrinking and start stacking, building the strings of cells vertically through the wafer instead of laying them out flat.
Toshiba described the approach in 2007 under the name BiCS.[34] Samsung was first to mass production, announcing 3D V-NAND with 24 stacked layers and 128 gigabits per die in August 2013.[33] Layer counts have climbed steeply ever since. SK hynix began making a 321-layer three-bit chip in November 2024 and a 321-layer four-bit version in August 2025, and has said it aims to reach 375 layers by the end of 2026.[7][35][36] Kioxia and SanDisk began sampling a 332-layer generation in July 2026.[37]
Stacking brought a second change. Rather than build the control circuitry on the same wafer as the memory, makers now often build the two separately, each on the process that suits it, and bond the wafers together. Kioxia calls its version CMOS directly Bonded to Array and YMTC calls its own Xtacking.[37][38] Samsung presented a design with more than 400 active layers at a conference in early 2025, using wafer bonding for the first time.[39]
The solid-state drive packages flash chips with a controller and presents itself to a computer as a disk. Early drives used the SATA interface designed for hard disks; the ones sold today mostly speak NVMe over PCI Express, a protocol written for flash rather than inherited from spinning platters.[4] Micron began mass-producing the first drives on the sixth generation of PCI Express in February 2026, at 28 gigabytes per second reading.[40]
Data-centre drives have grown very large. Kioxia announced a 245-terabyte drive in July 2025, built from a 32-high stack of four-bit dies — a single unit holding more than most organisations owned in total a decade ago.[41]
Phones and tablets use Universal Flash Storage, a JEDEC standard that bundles the flash and its controller into one small package. JEDEC published version 5.0 in February 2026, raising the ceiling to 10.8 gigabytes per second.[42] Cheaper and simpler devices still use the older eMMC standard, which has not been revised since 2015.[43]
SD and microSD cards remain the standard removable format. The SD Association's current specification, published in October 2023, defines an Express family that runs the card over PCI Express at up to four gigabytes per second.[44] CompactFlash in its original form is long retired; its association now maintains the CFexpress standards used in professional cameras.[45]
The newest category is aimed squarely at machine learning, where the bottleneck is feeding data to an accelerator fast enough. SK hynix set out a three-line plan in October 2025: one product tuned for speed, one for cheap bulk capacity, and one that stacks NAND vertically in the manner of high-bandwidth memory.[46] That last design, High Bandwidth Flash, is being standardised jointly with SanDisk through an Open Compute Project workstream announced in February 2026.[47] Kioxia has taken a different route, announcing in March 2026 a drive that lets a graphics processor reach flash directly.[48]
Five companies make almost all the world's flash. In the first quarter of 2026 Samsung Electronics led with US$13.5 billion of revenue, ahead of the SK hynix group including Solidigm at US$7.5 billion, with Kioxia, Micron Technology and SanDisk each near US$6 billion.[8] China's YMTC is the significant outsider, holding roughly 8% of supply at the end of 2024 and expanding despite having been placed on the United States export blacklist in December 2022.[49]
The line-up was redrawn in the middle of the decade. Kioxia, the direct descendant of Masuoka's Toshiba division, listed on the Tokyo Stock Exchange in December 2024.[50] SanDisk was separated from Western Digital and began trading on its own in February 2025.[51] SK hynix completed its purchase of Intel's flash business in March 2025, having run the acquired drive operation as Solidigm since 2021.[52] Kioxia and SanDisk, which have shared factories in Japan for years, extended that partnership to 2034 in January 2026.[53]
Flash has always been a cyclical business, and the current cycle is a shortage. AI servers now account for more than 40% of demand for flash bits, while phone and notebook production is falling. TrendForce puts the supply gap at 4% to 5%, with no return to balance before late 2027.[54] Prices have moved accordingly: contract prices for the single-level NAND used in industrial equipment rose 130% to 150% in the first half of 2026 alone.[55]
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